1. Field of the Invention
The present invention relates to electronic systems utilizing electronic device packaging techniques, and more particularly to electronic systems utilizing plastic, leadframe-type packages.
2. Description of the Related Technology
Electronic systems utilizing semiconductor devices such as integrated circuits have revolutionized the way modem society works and lives by making possible a level of technological sophistication unknown in the days of vacuum tubes and even discrete transistors. These electronic systems, which are building blocks for ever larger and more complex systems such as machines used in manufacture, transportation and the like. The sophistication of these electronic systems is the result of the complex functions handled by semiconductor devices, such as integrated circuits, making up the electronic system. An integrated circuit may comprise, on a small silicon chip, many thousand or even a million or more transistors, including associated diodes, resistors and capacitors, interconnected together to form complex electronic functions.
As used herein, the term "semiconductor device" refers to discrete or integrated circuit devices such as a silicon chip or die containing circuitry, and the term "semiconductor device package" refers to the associated packaging generally used for containing the semiconductor device (e.g., chip), including leads such as for connecting to a socket or a circuit board, and internal connections, such as bond wires or solder bump (micro-bump) connections, of the die to the leads.
In a typical modern semiconductor device package, a semiconductor die (device) is disposed within a package and is connected to conductive leads of the semiconductor device package by means of bond wires or "solder bump" (micro-bump) connections. The connections to the semiconductor die are typically accomplished via metallic connection points or "bond pads" (I/O pads) disposed on a planar surface of the die, around the periphery (along the edges) thereof in a "peripheral area". The peripheral area is a ring-shaped area on the surface of the die, essentially a narrow band between the edges of the die and the "interior area" of the die. The conductive leads of the semiconductor device package may be provided by a leadframe, such as in a molded plastic or TAB (Tape Automated Bonding) semiconductor device package, or by printed traces, such as in a ceramic or overmolded printed circuit board package. The conductive leads approach the semiconductor die within the semiconductor device package in a generally radial ("fan-in") pattern.
Typically, a leadframe is stamped (or etched) from a sheet of conductive material, simultaneously forming all of the conductive leads of the leadframe. Often, the leadframe is held together by sacrificial "bridges" between the leads, which are removed after the leadframe is assembled to a die and a package body is formed. The leads are then effectively separate. However, by virtue of their common mounting within a package body, they continue to behave as a unit. Alternatively, the leads can be formed on a non-conductive substrate, such as mylar, to form a tape automated bonding (TAB) packaged chip.
As the circuitry on a die operates, it dissipates power and heats up the die. Often, there is a mismatch between the thermal coefficients of expansion (TCE) of a semiconductor die and the leadframe (and package body) to which it is attached. This is especially troublesome where solder bump (micro-bump) connections are used to connect the die to the leadframe. (It is assumed that the heating of the die as it operates is fairly uniform). Generally, as temperature rises, the die expands about its "centroid" (center of mass) or around a circuit element that produces heat, as do the leadframe and package body. However, the die expands at a different rate than the leadframe and package body, causing a great deal of mechanical stress at the interface between the leadframe and the bond pads (the solder bump connections). This stress creates a tendency of the bond pads to tear away from the die, resulting in a failed device.
Clearly, if heat can be carried away from the die at a sufficient rate, much of the thermal expansion can be prevented, and consequent undesirable behavior avoided. The package body itself is typically thermally coupled to the semiconductor die, and acts to some degree as a heat sink. Many techniques are known in the art for drawing heat away from a packaged semiconductor device, and typically include a separate heat sink element. However, present heat-sinking techniques are generally either elaborate or only partially effective. Some such techniques attempt to provide a high degree of thermal coupling of a large thermal mass, such as a finned heat sink, directly to the die. These techniques are often cumbersome, expensive, and tend to dramatically increase the size (and cost) of the semiconductor package.
Other techniques are directed to drawing heat away from the exterior of the semiconductor device package. Such techniques are often less expensive, but still tend to increase the effective size of the package. Further, while some measure of cooling (heat draw) is provided by these techniques, there is a thermal resistance between the semiconductor die and the package body which can permit, in many cases, a significant difference between the die temperature and the temperature at the exterior of the package body.
On any thermally expanding body, the further a point on the body is from the centroid, the greater the absolute distance it travels (displaces) during expansion. Since semiconductor dies are typically rectangularly shaped and the bond pads are typically disposed along the edges of the rectangular shape (in the peripheral area), the bond pads undergo a fairly large amount of absolute displacement as compared to points located closer to the center of the die. Any bond pads located at the corners of the die, being furthest from the centroid, undergo the greatest displacement during thermal expansion. As a consequence of the absolute thermal displacements that any two different points undergo on the surface of the die, they undergo differential thermal displacements relative to one another. The further from one another that any two points on the surface of an expanding die are, the greater the differential thermal displacement between them. The leadframe and package body combination also expands about its centroid, albeit at a different rate. The center of expansion of the leadframe/package body combination is generally located fairly close to the centroid of the die, since the die is the heat source which causes the expansion. As a result, any differential thermal displacement causing mechanical stress at the bond pads of a semiconductor device is greatest at the corners of the die. The common practice of disposing bond pads along the edges of the die, therefore, would seem to create the worst possible circumstances from the point of view of thermal expansion.
One of the most significant reasons that bond pads are typically disposed about the edges (periphery) of a die is that it permits a relatively large number of I/O connections to the die without causing connections to cross one another. Current trends are towards providing smaller bond pads so that even greater numbers of connections to the die may be accommodated. Unfortunately, such smaller connections (i.e., smaller bond pads) tend to be even more fragile than "ordinary" (larger) size connections, making such techniques even more prone to thermal stress problems and device failure.
Another problem with locating bond pads along the periphery of a die is that many of the connections are made to circuitry that lies well within the interior of the die, requiring that the signals from that circuitry must travel a relatively great distance within the die along the die's minute wiring structures (conductive lines) before they reach the bond pad connections at the periphery of the die. Hence, a "pad buffer" circuit is usually provided at or near a bond pad associated with an output signal on order to buffer the output signal at the bond pad. This can contribute to timing "skew," or differences in signal timing due to different wiring delays, particularly for very high speed circuits. The wiring structures (conductive lines) with a die are extremely small and exhibit relatively high resistance. Even a tiny bond wire is a massive conductor compared to the relatively tiny interconnections on a die.
Attention is directed to the following U.S. Patents, incorporated herein by reference, and of general interest with respect to leadframe-type semiconductor device packages and methods of manufacture: U.S. Pat. No. 4,701,999, issued Oct. 27 1987 to Palmer; U.S. Pat. No. 4,774,635, issued Sep. 27, 1988 to Greenberg et al.; U.S. Pat. No. 4,894,704, issued Jan. 16,1990 to Endo; U.S. Pat. No. 4,897,602, issued Jan. 30, 1990 to Lin et al.; and U.S. Pat. No. 5,051,813, issued Sep. 24, 1991 to Schneider et al.
Attention is further directed to the following U.S. Patents, incorporated herein by reference, and of general interest with respect to micro-bump (e.g., solder bump) bonding: U.S. Pat. No. 3,429,040, issued Feb. 25, 1969 to Miller; U.S. Pat. No. 3,811,186, issued May 21, 1974 to Larnerd et al.; U.S. Pat. No. 3,871,014, issued Mar. 11, 1975 to King et al.; U.S. Pat. No. 3,984,860, issued Oct. 5, 1976 to Logue; U.S. Pat. No. 4,190,855, issued Feb. 26, 1980 to Inoue; U.S. Pat. No. 4,772,936, issued Sep. 20, 1988 to Reding et al.; U.S. Pat. No. 4,803,546, issued Feb. 7, 1989 to Sugimoto et al.; U.S. Pat. No. 4,825,284, issued Apr. 25, 1989 to Soga et al.; U.S. Pat. No. 4,926,241, issued May 15, 1990 to Carey; and U.S. Pat. No. 4,970,575, issued Nov. 13, 1990 to Soga et al.
Other information relating to microbump bonding techniques may be found in Japanese Patent number 61-145838A issued on Jul. 3, 1986 to Kishio Yokouchi, and in "LED Array Modules by New Technology Microbump Bonding Method," by Hatada, Fujimoto, Ochi, and Ishida, IEEE Trans. Comp., Hybrids, and Manuf Tech., Volume 13 no. 3, Sep. 1990, incorporated by reference herein.